/**
 * @file    GT9881_RINGBUFFER.h
 * @author  Giantec-Semi ATE
 * @brief   CMSIS GT98xx Device Peripheral Access Layer Header File
 * @version 0.1
 * 
 * @copyright Copyright (c) 2021 Giantec-Semi
 * 
 */

#ifndef GT98XX_DEVICE_GT9881_RINGBUFFER_H_
#define GT98XX_DEVICE_GT9881_RINGBUFFER_H_

#ifdef __cplusplus
    extern "C" {
#endif /* __cplusplus */

#include "gt9881.h"

/**
 * @addtogroup Peripheral_Registers_Structures
 * @{
 */
/**
 * @struct RingbufferTypedef
 * @brief RingBuffer Registers structure define
 */
typedef struct
{
  __IO uint32_t RB_EN;                   ///< Ring buffer enable register 
       uint32_t DATA_READY;              ///< Data ready register 
  __IO uint32_t CTL;                     ///< Control registger 
  __IO uint32_t STATE;                   ///< State register 
  __IO uint32_t BUFFER1_0;               ///< Buffer1 register0 
  __IO uint32_t BUFFER1_1;               ///< Buffer1 register1 
  __IO uint32_t BUFFER1_2;               ///< Buffer1 register2 
  __IO uint32_t BUFFER1_3;               ///< Buffer1 register3 
  __IO uint32_t BUFFER0_0;               ///< Buffer0 register0 
  __IO uint32_t BUFFER0_1;               ///< Buffer0 register1 
  __IO uint32_t BUFFER0_2;               ///< Buffer0 register2 
  __IO uint32_t BUFFER0_3;               ///< Buffer0 register3 
  __IO uint32_t TMR;                     ///< 0.5ms cycle register 
} RingbufferTypedef;
/** @} Peripheral_Registers_Structures */

/**
 * @addtogroup Peripheral_Memory_Map
 * @{
 */
#define RINGBUFFER_BASE               (PERIPH_BASE + 0xC000UL)    ///< RINGBUFFER base address
/** @} Peripheral_Memory_Map */

/**
 * @addtogroup Peripheral_Declaration
 * @{
 */
#define RINGBUFFER                ((RINGBUFFER_TypeDef*)RINGBUFFER_BASE)      ///< RINGBUFFER operator
/** @} Peripheral_Declaration */


/**
 * @defgroup  RINGBUFFER_Bitmap RingBuffer Bitmap
 * @ingroup   Peripheral_Registers_Bits_Definition
 * @brief     Bitmap of RingBuffer Registers
 * @{
 */

#define RINGBUFFER_RB_EN_Pos                    (0U)
#define RINGBUFFER_RB_EN_Msk                    (0x1UL << RINGBUFFER_RB_EN_Pos)
/**
 * @def     RINGBUFFER_RB_EN
 * @brief   RingBuffer Enable
 * <pre>
 * @a 0 : RingBuffer Disabled (default)
 * @a 1 : RingBuffer Enabled
 * </pre>
 */
#define RINGBUFFER_RB_EN                        RINGBUFFER_RB_EN_Msk

#define RINGBUFFER_DATA_READY_Pos               (0U)
#define RINGBUFFER_DATA_READY_Msk               (0x1UL << RINGBUFFER_DATA_READY_Pos)
/**
 * @def     RINGBUFFER_DATA_READY
 * @brief   Automatically Update to 1 when valid data packet in Buffer0. Writing 0 to this bit to clear DATA_READY bit
 * <pre>
 * @a 0 : Buffer0 has no valid data packet
 * @a 1 : Buffer0 has VALID data packet, ready to be moved to buffer1
 * </pre>
 */
#define RINGBUFFER_DATA_READY                   RINGBUFFER_DATA_READY_Msk

#define RINGBUFFER_CTL_SAMPLE_TIME_Pos          (0U)
#define RINGBUFFER_CTL_SAMPLE_TIME_Msk          (0xFFUL << RINGBUFFER_CTL_SAMPLE_TIME_Pos)
/**
 * @def     RINGBUFFER_CTL_SAMPLE_TIME
 * @brief   RingBuffer SAMPLE_TIME constant
 * <pre>
 * @a 2'h00~2'h03 : Not supported
 * @a 2'h04~2'hFF : 2.0ms~127.5ms
 * </pre>
 */
#define RINGBUFFER_CTL_SAMPLE_TIME              RINGBUFFER_CTL_SAMPLE_TIME_Msk

#define RINGBUFFER_CTL_CHECK_TIME_Pos           (8U)
#define RINGBUFFER_CTL_CHECK_TIME_Msk           (0xFFUL << RINGBUFFER_CTL_CHECK_TIME_Pos)
/**
 * @def     RINGBUFFER_CTL_CHECK_TIME
 * @brief   RingBuffer CHECK_TIME constant
 * <pre>
 * @a 2'h00~2'h07 : Not supported
 * @a 2'h08~2'hFF : 4.0ms~127.5ms
 * </pre>
 */
#define RINGBUFFER_CTL_CHECK_TIME               RINGBUFFER_CTL_CHECK_TIME_Msk

#define RINGBUFFER_CTL_VSYNC_Pos                (16U)
#define RINGBUFFER_CTL_VSYNC_Msk                (0x3UL << RINGBUFFER_CTL_VSYNC_Pos)
/**
 * @def     RINGBUFFER_CTL_VSYNC
 * @brief   VSYNC trigger
 * <pre>
 * @a 1'h0 : VSYNC triggered by falling-edge (default)
 * @a 1'h1 : VSYNC triggered by rising-edge
 * @a 1'h2 : VSYNC triggered by high voltage level
 * @a 1'h3 : VSYNC triggered by low voltage level
 * </pre>
 */
#define RINGBUFFER_CTL_VSYNC                    RINGBUFFER_CTL_VSYNC_Msk

#define RINGBUFFER_STATE_TIMESTAMP_Pos          (0U)
#define RINGBUFFER_STATE_TIMESTAMP_Msk          (0xFFUL << RINGBUFFER_STATE_TIMESTAMP_Pos)
/**
 * @def     RINGBUFFER_STATE_TIMESTAMP
 * @brief   The timestamp of the 1st data packet of current transfer.
 */
#define RINGBUFFER_STATE_TIMESTAMP              RINGBUFFER_STATE_TIMESTAMP_Msk

#define RINGBUFFER_STATE_DATALENTH_Pos          (8U)
#define RINGBUFFER_STATE_DATALENTH_Msk          (0xFUL << RINGBUFFER_STATE_DATALENTH_Pos)
/**
 * @def     RINGBUFFER_STATE_DATALENTH
 * @brief   Data length, recording number of ready data packet.
 * <pre>
 * Update when AP reads data_ready=1
 * </pre>
 */
#define RINGBUFFER_STATE_DATALENTH              RINGBUFFER_STATE_DATALENTH_Msk

#define RINGBUFFER_STATE_FIRMWARE_Pos           (12U)
#define RINGBUFFER_STATE_FIRMWARE_Msk           (0xFUL << RINGBUFFER_STATE_FIRMWARE_Pos)
/**
 * @def     RINGBUFFER_STATE_FIRMWARE
 * @brief   Firmware status, to be configured by software.
 */
#define RINGBUFFER_STATE_FIRMWARE               RINGBUFFER_STATE_FIRMWARE_Msk

#define RINGBUFFER_BUFFER1_0_Pos                (0U)
#define RINGBUFFER_BUFFER1_0_Msk                (0xFFFFFFFFUL << RINGBUFFER_BUFFER1_0_Pos)
/**
 * @def     RINGBUFFER_STATE_FIRMWARE
 * @brief   FIFO tail Byte 0~3 in RingBuffer Buffer1
 */
#define RINGBUFFER_BUFFER1_0                    RINGBUFFER_BUFFER1_0_Msk

#define RINGBUFFER_BUFFER1_1_Pos                (0U)
#define RINGBUFFER_BUFFER1_1_Msk                (0xFFFFFFFFUL << RINGBUFFER_BUFFER1_1_Pos)
/**
 * @def     RINGBUFFER_STATE_FIRMWARE
 * @brief   FIFO tail Byte 4~7 in RingBuffer Buffer1
 */
#define RINGBUFFER_BUFFER1_1                    RINGBUFFER_BUFFER1_1_Msk

#define RINGBUFFER_BUFFER1_2_Pos                (0U)
#define RINGBUFFER_BUFFER1_2_Msk                (0xFFFFFFFFUL << RINGBUFFER_BUFFER1_2_Pos)
/**
 * @def     RINGBUFFER_STATE_FIRMWARE
 * @brief   FIFO tail Byte 8~11 in RingBuffer Buffer1
 */
#define RINGBUFFER_BUFFER1_2                    RINGBUFFER_BUFFER1_2_Msk

#define RINGBUFFER_BUFFER1_3_Pos                (0U)
#define RINGBUFFER_BUFFER1_3_Msk                (0xFFFFFFFFUL << RINGBUFFER_BUFFER1_3_Pos)
/**
 * @def     RINGBUFFER_STATE_FIRMWARE
 * @brief   FIFO tail Byte 12~15 in RingBuffer Buffer1
 */
#define RINGBUFFER_BUFFER1_3                    RINGBUFFER_BUFFER1_3_Msk

#define RINGBUFFER_BUFFER0_0_Pos                (0U)
#define RINGBUFFER_BUFFER0_0_Msk                (0xFFFFFFFFUL << RINGBUFFER_BUFFER1_0_Pos)
/**
 * @def     RINGBUFFER_STATE_FIRMWARE
 * @brief   FIFO tail Byte 0~3 in RingBuffer Buffer0
 */
#define RINGBUFFER_BUFFER0_0                    RINGBUFFER_BUFFER1_0_Msk

#define RINGBUFFER_BUFFER0_1_Pos                (0U)
#define RINGBUFFER_BUFFER0_1_Msk                (0xFFFFFFFFUL << RINGBUFFER_BUFFER1_1_Pos)
/**
 * @def     RINGBUFFER_STATE_FIRMWARE
 * @brief   FIFO tail Byte 4~7 in RingBuffer Buffer0
 */
#define RINGBUFFER_BUFFER0_1                    RINGBUFFER_BUFFER1_1_Msk

#define RINGBUFFER_BUFFER0_2_Pos                (0U)
#define RINGBUFFER_BUFFER0_2_Msk                (0xFFFFFFFFUL << RINGBUFFER_BUFFER1_2_Pos)
/**
 * @def     RINGBUFFER_STATE_FIRMWARE
 * @brief   FIFO tail Byte 8~11 in RingBuffer Buffer0
 */
#define RINGBUFFER_BUFFER0_2                    RINGBUFFER_BUFFER1_2_Msk

#define RINGBUFFER_BUFFER0_3_Pos                (0U)
#define RINGBUFFER_BUFFER0_3_Msk                (0xFFFFFFFFUL << RINGBUFFER_BUFFER1_3_Pos)
/**
 * @def     RINGBUFFER_STATE_FIRMWARE
 * @brief   FIFO tail Byte 12~15 in RingBuffer Buffer0
 */
#define RINGBUFFER_BUFFER0_3                    RINGBUFFER_BUFFER1_3_Msk

#define RINGBUFFER_TMR_Pos                      (0U)
#define RINGBUFFER_TMR_Msk                      (0xFFFFFFFFUL << RINGBUFFER_TMR_Pos)
/**
 * @def     RINGBUFFER_TMR
 * @brief   SPI Timer
 * <pre>
 * TMR * cycle_apb = 0.5ms
 * Defaulf value : 32'h5dc4
 * </pre>
 */
#define RINGBUFFER_TMR                          RINGBUFFER_TMR_Msk

/** @}  RINGBUFFER_Bitmap */
/** @}  RINGBUFFER_REG */

#endif  /* __GT9881_RINGBUFFER_H__ */

